There are a number of situations when it is desirable to translate signals with small voltage swings into signals with larger voltage swings. For a differential input signal, the typical solution uses a sense amplifier (SA). In order to use the SA in the case of non-differential signals, a special reference voltage is needed. Typically, SA's are optimized for sensing very small signals at the expense of additional delay. Additionally, both the SA and the reference voltage generator may contain many transistors which may require a large circuit area.
FIG. 1 shows a typical circuit 100 used to provide level translation. The circuit 100 comprises NFETs 102, 104 and 106. The circuit 100 also comprises cross-coupled PFETs 108 and 110, and PFET 112. A serial connection is formed where the drain of the NFET 102 is coupled to the drain of the PFET 108. The upper NFET 102 source and the lower NFET 104 drain are connected to the drain of the additional PFET 112. The gate of the PFET 112 is connected to the gates of the NFET 102 and 104, and to an input 114. A reduced supply voltage (Vdd1) is fed to the source of this additional PFET 112. The FETs 102, 104, 106 and 112 have small threshold voltages (0.2 * Vdd1) while the FETs 108 and 110 have large threshold voltages (0.2 * Vdd2), where Vdd2 is larger that Vdd1. while the FETs 108 and 110 have large threshold voltages (0.2 * Vdd2), where Vdd2 is larger that Vdd1.
The circuit 100 has significant problems regarding switching speed. In the quiescent state (where the output equals zero), the PFET 108 is opened and the gate of PFET 110 is charged to Vdd2. To switch on the PFET 110, the capacitance of node 116 should be discharged to ground. Since the discharge current is the difference between the current through the NFET 102 and the current through the PFET 108, the PFET 110 will hardly tum on, thereby resulting in a large turn on delay. Similarly, when the NFET 106 turns on, part of its drain current passes through PFET 110 instead of the output load (since the capacitance of the PFET 110 gate should be charged by the PFET 108 turned on by the NFET 106) which then leads to a large turn off delay. This situation is typical for cases where the input and output stages have different power supplies.
The second drawback of the circuit 100 is that there are significant crowbar currents: through FETs 108, 102, and 104 during the switching on transition and through FETs 110 and 106 during switching off transition, thus wasting power. In addition, the small threshold of the NFET 106 contributes to a large leakage current in the off state thus increasing standby power.